HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 85

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Altera Corporation
September 2008
Tables 4–45
the dedicated circuitry used for interfacing with external memory
devices.
Table 4–46
HardCopy II DQS delay buffer. Multiply the number of delay buffers that
you are using in the DQS logic block to get the maximum delay
achievable in your system. For example, if you implement a 90° phase
shift at 200 MHz, you use three delay buffers in mode 2. The maximum
achievable delay from the DQS block is then 3 × .416 ps = 1.248 ns.
Notes to
(1)
(2)
DLL Frequency Mode Maximum Delay Per Delay Buffer
Table 4–45. DLL Frequency Range Specifications
Table 4–46. DQS Delay Buffer Maximum Delay in Fast Timing Model
Table 4–47. DQS Period Jitter Specifications for DLL-Delayed Clock
(tDQS_JITTER)
Frequency Mode
Number of DQS Delay Buffer
Peak-to-peak period jitter on the phase shifted DQS clock.
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
1, 2, 3
Table
0
0
1
2
3
lists the maximum delay in the fast timing model for the
through
Stages
4–47:
1
2
3
4
Note (1)
(2)
4–51
contain HardCopy II device specifications for
Frequency Range
100 to 175
150 to 230
200 to 310
240 to 350
External Memory Interface Specifications
Commercial
0.833
0.416
110
130
160
80
Industrial
Resolution (Degrees)
110
130
180
210
22.5
30
30
36
Unit
ns
ns
Unit
ps
ps
ps
ps
4–43