HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 80

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
4–38
Notes to
(1)
(2)
(3)
f
f
TCCS
SW
Output jitter
Output t
Output t
t
DPA run length
DPA jitter tolerance
(peak-to-peak)
DPA lock time
HSDR
HSDRDPA
DUTY
Table 4–41. HardCopy II High-Speed I/O Specifications for HC210, HC220, HC230 and HC240 Devices
Note (1)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input
clock frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) used. The I/O differential buffer and input register do not
have a minimum toggle rate.
(data rate)
RISE
FALL
(DPA data rate)
Symbol
Table
(Part 2 of 2)
4–41:
Parallel Rapid I/O
J = 4 to 10 (LVDS, HyperTransport technology)
J = 4 to 10 (LVDS, HyperTransport technology)
Miscellaneous
J = 2 (LVDS, HyperTransport technology)
Standard
SPI4
—
—
—
All differential I/O standards
All differential I/O standards
All differential standards
All differential standards
J = 1 (LVDS only)
Conditions
0000000000
1111111111
10010000
10010000
10101010
10101010
—
—
—
—
Training
Pattern
—
Transition
Density
100%
10%
25%
50%
—
—
0.44
Min
150
150
330
256
256
256
256
256
(3)
(3)
—
45
—
—
—
—
—
—
Typ
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Altera Corporation
1,040
1,040
6,400
Max
200
760
500
190
160
180
55
September 2008
—
—
—
—
—
—
—
—
—
Number of
repetitions
Mbps
Mbps
Mbps
Mbps
Unit
ps
ps
ps
ps
ps
UI
UI
%