HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 22
HC230
Manufacturer Part Number
HC230
Description
HardCopy II Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.HC230.pdf
(228 pages)
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HardCopy Series Handbook, Volume 1
I/O Structure and
Features
2–14
Preliminary
Number of global clock networks
Number of regional clock networks
Global clock input sources
Regional clock input sources
Number of unique clock sources in a quadrant
Number of unique clock sources in the entire device
Power-down mode
Clocking regions for high fan-out applications
Table 2–8. Clock Network Resources and Features Available in HardCopy II Devices
Resources and Features
Clock Networks
There are 16 clock pins (CLK[15..0]) in HardCopy II devices that can
drive either the global- or regional-clock networks. The CLK pins can
drive clock ports or data inputs.
HardCopy II devices provide 16 dedicated global-clock networks and
32 regional-clock networks; the same as in Stratix II FPGAs. These clocks
are organized to provide 24 unique clock sources per device quadrant
with low skew and delay. This clocking scheme provides up to 48 unique
clock domains within the entire HardCopy II device.
clock resources and features available in HardCopy II devices.
HardCopy II devices also support the same features as the Stratix II clock
control block, which is available for each global- and regional-clock
network. The control block has two functions:
■
■
The structure and features of the HardCopy II IOE remains the same as in
Stratix II. Any feature implemented in Stratix II IOEs can be migrated to
Hardcopy II IOEs.
Clock source selection (dynamic selection for global clocks):
You user can either dynamically select between two PLL outputs,
between two clock pins (CLKp or CLKn), or a combination of the
clock pins or PLL outputs.
Clock power-down (dynamic clock enable or disable):
In HardCopy II devices, you can dynamically turn the clock off or on
in user-mode.
16
32
Clock input pins, PLL outputs, logic array
Clock input pins, PLL outputs, logic array
24 (16 global clocks and 8 regional clocks)
48 (16 global clocks and 32 regional clocks)
Global- and regional-clock networks,
dual-regional-clock region
Quadrant region, dual-regional, entire device via global-
or regional-clock networks
Availability
Table 2–8
Altera Corporation
September 2008
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