HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 200
HC230
Manufacturer Part Number
HC230
Description
HardCopy II Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.HC230.pdf
(228 pages)
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HardCopy Series Handbook, Volume 1
8–12
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Differential
SSTL-18 class I
and II output
1.8-V differential
HSTL class I
and II input
1.8-V differential
HSTL class I
and II output
1.5-V differential
HSTL class I
and II input
1.5-V differential
HSTL class I
and II output
LVDS input
LVDS output
HyperTransport
technology input
HyperTransport
technology
output
LVPECL input
Table 8–7. Hardcopy II Supported I/O Standards of Input Clocks, Clock Out, and PLL Feedback (Part 2 of 2)
I/O Standard
CLK8 and CLK10 pins on HC210, HC220, and HC230 devices do not support differential standards LVDS and
HyperTransport technology. Only LVTTL is supported on these CLK pins for these devices.
CLK[4..7] pins on HC210 and HC220 devices do not support SSTL, HSTL, differential SSTL, and HSTL input or
output.
HC230 only has two fast PLL clocks, FPLL[7..8]CLK. HC240 has four FPLL clocks, FPLL[7..10]CLK.
HC210 and HC220 PLL6_OUT pins do not support SSTL, HSTL, differential SSTL, and HSTL input or output.
HC210 and HC220 PLL6_FB pins do not support SSTL, HSTL, differential SSTL, and HSTL input or output.
Pseudo-differential HSTL and SSTL inputs only use the positive polarity input in the speed path. The negative
input is not connected internally. Pseudo-differential HSTL and SSTL outputs use two single-ended outputs with
the second output programmed as inverted. This is similar to a Stratix II device implementation.
This is not supported.
Table
8–7:
Differential
Differential
Differential
Differential
Differential
differential
differential
differential
differential
differential
Pseudo
Pseudo
Pseudo
Pseudo
Pseudo
Type
(6)
(6)
(6)
(6)
(6)
3.3/2.5/
3.3/2.5/
3.3/2.5/
1.8/1.5
1.8/1.5
1.8/1.5
V
Input
2.5
2.5
CCIO
Level (V)
Output
2.5V
1.8
1.8
1.5
2.5
(7)
CLK[0..3,
8..11]
v
v
(1)
CLK[4..7,
12..15]
(2)
v
v
v
v
v
FPLL_CLK
(3)
v
v
PLL_OUT
Altera Corporation
(4)
v
v
v
v
v
v
September 2008
PLL_FB
(5)
v
v
v
v
v
v
v
v
v
v
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