ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 103

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

12.12 Memory access instructions
12.12.1
12.12.1.1
12.12.1.2
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
ADR
Syntax
Operation
Table 12-17
Table 12-17. Memory access instructions
Load PC-relative address.
where:
cond
Rd
label
ADR determines the address by adding an immediate value to the PC, and writes the result to
the destination register.
ADR produces position-independent code, because the address is PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure that
bit[0] of the address you generate is set to1 for correct execution.
Mnemonic
ADR
CLREX
LDM{mode}
LDR{type}
LDR{type}
LDR{type}T
LDR
LDREX{type}
POP
PUSH
STM{mode}
STR{type}
STR{type}
STR{type}T
STREX{type}
ADR{cond} Rd, label
shows the memory access instructions:
is an optional condition code, see
is the destination register.
is a PC-relative expression. See
Brief description
Load PC-relative address
Clear Exclusive
Load Multiple registers
Load Register using immediate
offset
Load Register using register offset
Load Register with unprivileged
access
Load Register using PC-relative
address
Load Register Exclusive
Pop registers from stack
Push registers onto stack
Store Multiple registers
Store Register using immediate
offset
Store Register using register offset
Store Register with unprivileged
access
Store Register Exclusive
“PC-relative expressions” on page
“Conditional execution” on page
See
“ADR” on page 103
“CLREX” on page 114
“LDM and STM” on page 110
“LDR and STR, immediate offset” on
page 104
“LDR and STR, register offset” on page
106
“LDR and STR, unprivileged” on page
107
“LDR, PC-relative” on page 108
“LDREX and STREX” on page 112
“PUSH and POP” on page 111
“PUSH and POP” on page 111
“LDM and STM” on page 110
“LDR and STR, immediate offset” on
page 104
“LDR and STR, register offset” on page
106
“LDR and STR, unprivileged” on page
107
“LDREX and STREX” on page 112
SAM3X/A
SAM3X/A
100.
99.
103
103