ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 215

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

Implementation-specific
Index register
Instruction cycle count
Interrupt handler
Interrupt vector
Little-endian (LE)
Little-endian memory
Load/store architecture
Memory Protection Unit (MPU)
Prefetching
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the
option chosen does not affect software compatibility.
In some load and store instruction descriptions, the value of this register is used as an offset to
be added to or subtracted from the base register value to form the address that is sent to mem-
ory. Some addressing modes optionally enable the index register value to be shifted prior to the
addition or subtraction.
See also
The number of cycles that an instruction occupies the Execute stage of the pipeline.
A program that control of the processor is passed to when an interrupt occurs.
One of a number of fixed addresses in low memory, or in high memory if high vectors are config-
ured, that contains the first instruction of the corresponding interrupt handler.
Byte ordering scheme in which bytes of increasing significance in a data word are stored at
increasing addresses in memory.
See also
Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the
word at that address
a byte at a halfword-aligned address is the least significant byte within the halfword at that
address.
A processor architecture where data-processing operations only operate on register contents,
not directly on memory contents.
Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
In pipelined processors, the process of fetching instructions from memory to fill up the pipeline
before the preceding instructions have finished executing. Prefetching an instruction does not
mean that the instruction has to be executed.
“Base register”
“Little-endian memory”
,
“Endianness”
SAM3X/A
SAM3X/A
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