ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 1141
ATSAM3X4EA-AU
Manufacturer Part Number
ATSAM3X4EA-AU
Description
ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
Manufacturer
Atmel
Datasheet
1.ATSAM3X8EA-AU.pdf
(1467 pages)
Specifications of ATSAM3X4EA-AU
Rohs
yes
Core
ARM Cortex M3
Processor Series
SAM3X
Data Bus Width
32 bit
Maximum Clock Frequency
84 MHz
Program Memory Size
256 KB
Data Ram Size
64 KB
On-chip Adc
Yes
Operating Supply Voltage
2.4 V to 3.6 V
Operating Temperature Range
- 40 C to +85 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Factory Pack Quantity
60
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This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as UOTGHS_DEVEPTIMRx.FIFOCON
when the current bank is full. This triggers a PEP_x interrupt if UOTGHS_DEVEPTIMRx.RXOUTE is one.
Shall be cleared for isochronous, bulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will
acknowledge the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO and clears the UOTGHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT end-
point is composed of multiple banks, this also switches to the next bank. The UOTGHS_DEVEPTISRx.RXOUTI and
UOTGHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.
UOTGHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing UOTGHS_DEVEPTIMRx.FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
• TXINI: Transmitted IN Data Interrupt
This bit is set for control endpoints, when the current bank is ready to accept a new IN packet. This triggers a PEP_x inter-
rupt if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.
This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as UOTGHS_DEVEPTIMRx.FIFOCON
when the current bank is free. This triggers a PEP_x interrupt if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the end-
point FIFO.
The user then writes into the FIFO and clears the UOTGHS_DEVEPTIMRx.FIFOCON bit to allow the UOTGHS to send the
d a t a . I f t h e I N e n d p o i n t i s c o m p o s e d o f m u l t i p l e b a n k s , t h i s a l s o s w i t c h e s t o t h e n e x t b a n k . T h e
UOTGHS_DEVEPTISRx.TXINI and UOTGHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status
of the next bank.
UOTGHS_DEVEPTISRx.TXINI shall always be cleared before clearing UOTGHS_DEVEPTIMRx.FIFOCON.
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
SAM3X/A
SAM3X/A
1141
1141
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