ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 228

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

14.4
14.4.1
14.4.2
14.4.2.1
228
228
Functional Description
SAM3X/A
SAM3X/A
Reset Controller Overview
NRST Manager
NRST Signal or Interrupt
The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at
Slow Clock and generates the following reset signals:
These reset signals are asserted by the Reset Controller, either on external events or on soft-
ware action. The Reset State Manager controls the generation of reset signals and provides a
signal to the NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling
external device resets.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con-
troller, is powered with VDDIO, so that its configuration is saved as long as VDDIO is on.
After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR.
When ERSTL has elapsed, the pin behaves as an input and all the system is held in reset if
NRST is tied to GND by an external signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the
Reset State Manager.
Figure 14-2. NRST Manager
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low,
a User Reset is reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of
NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.
As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only
when RSTC_SR is read.
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
NRST
Figure 14-2
RSTC_SR
nrst_out
URSTS
NRSTL
shows the block diagram of the NRST Manager.
External Reset Timer
RSTC_MR
RSTC_MR
ERSTL
URSTEN
RSTC_MR
URSTIEN
interrupt
sources
Other
user_reset
exter_nreset
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
rstc_irq