ATSAM3X4EA-AU Atmel, ATSAM3X4EA-AU Datasheet - Page 113

• Manufacturer Part Number: ATSAM3X4EA-AU
• Description: ARM Microcontrollers - MCU QFP144,GREEN, IND TEMP, MRL A
• Manufacturer: Atmel

Specifications of ATSAM3X4EA-AU

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: SAM3X
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 84 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 64 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 3.6 V
• Operating Temperature Range: - 40 C to +85 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 60

12.12.8.2
12.12.8.3
12.12.8.4
12.12.8.5
11057B–ATARM–28-May-12
11057B–ATARM–28-May-12
try
MOV
LDREX
CMP
ITT
STREXEQ R0, R1, [LockAddr]
CMPEQ
BNE
....
Operation
Restrictions
Condition flags
Examples
R1, #0x1
R0, [LockAddr]
R0, #0
EQ
R0, #0
try
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory
address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a
memory address. The address used in any Store-Exclusive instruction must be the same as the
address in the most recently executed Load-exclusive instruction. The value stored by the Store-
Exclusive instruction must also have the same data size as the value loaded by the preceding
Load-exclusive instruction. This means software must always use a Load-exclusive instruction
and a matching Store-Exclusive instruction to perform a synchronization operation, see
chronization primitives” on page 78
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does
not perform the store, it writes 1 to its destination register. If the Store-Exclusive instruction
writes 0 to the destination register, it is guaranteed that no other process in the system has
accessed the memory location between the Load-exclusive and Store-Exclusive instructions.
For reasons of performance, keep the number of instructions between corresponding Load-
Exclusive and Store-Exclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.
In these instructions:
These instructions do not change the flags.
• do not use PC
• do not use SP for Rd and Rt
• for STREX, Rd must be different from both Rt and Rn
• the value of offset must be a multiple of four in the range 0-1020.
; Initialize the ‘lock taken’ value
; Load the lock value
; Is the lock free?
; IT instruction for STREXEQ and CMPEQ
; Try and claim the lock
; Did this succeed?
; No – try again
; Yes – we have the lock
SAM3X/A
SAM3X/A
“Syn-
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