DS26514G Maxim Integrated, DS26514G Datasheet - Page 172
DS26514G
Manufacturer Part Number
DS26514G
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26514G.pdf
(305 pages)
Specifications of DS26514G
Part # Aliases
90-26514-G00
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being
used.
Bit 6: Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
Bit 5: Receive Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used.
Bit 4: Receive Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used.
Bit 3: Receive Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used.
Bit 2: Receive Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used.
Bit 1: Receive Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used.
Bit 0: Receive Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being
used.
Register Name:
Register Description:
Register Address:
CH8
CH16
CH24
CH32
Setting any of the CH1 through CH32 bits in the RHCS1 through RHCS4 registers will enable the Receive HDLC
clock for the associated channel time, and allow mapping of the selected channel data into the HDLC-256 Port.
Multiple, or all channels may be selected simultaneously.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7 : Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used.
Bit 6 : Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used.
Bit 5 : Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used.
Bit 4 : Receive Channel Bit 5 Suppress / Sa4 Bit Suppress (BSE5). Set to one to stop this bit from being used
Bit 3 : Receive Channel Bit 4 Suppress / Sa5 Bit Suppress (BSE4). Set to one to stop this bit from being used
Bit 2 : Receive Channel Bit 3 Suppress / Sa6 Bit Suppress (BSE3). Set to one to stop this bit from being used
19-5856; Rev 4; 5/11
(MSB)
CH7
CH15
CH23
CH31
RHBSE
BPBSE8
7
8
0
7
0
CH6
CH14
CH22
CH30
RHBSE
BPBSE7
RBPBS
Receive BERT Port Bit Suppress Register
08Bh + (200h x (n - 1)) : where n = 1 to 4
RHCS1, RHCS2, RHCS3, RHCS4
Receive HDLC-256 Channel Select Registers
0DCh, 0DDh, 0DEh, 0DFH
RHBS
Receive HDLC-256 Bit Suppress Register
08DH
6
7
0
6
0
CH5
CH13
CH21
CH29
RHBSE
5
6
0
BPBSE6
5
0
CH4
CH12
CH20
CH28
RHBSE
4
5
0
BPBSE5
4
0
CH3
CH11
CH19
CH27
RHBSE
3
4
0
BPBSE4
CH2
CH10
CH18
CH26
RHBSE
3
0
2
3
0
DS26514 4-Port T1/E1/J1 Transceiver
CH1
CH9
CH17
CH25
BPBSE3
RHBSE
(LSB)
1
2
0
2
0
RHCS1
RHCS2
RHCS3
RHCS4
RHBSE1
BPBSE2
0
0
1
0
BPBSE1
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0
0
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