DS26514G Maxim Integrated, DS26514G Datasheet - Page 222
DS26514G
Manufacturer Part Number
DS26514G
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26514G.pdf
(305 pages)
Specifications of DS26514G
Part # Aliases
90-26514-G00
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7 : Transmit HDLC-256 Mode Select (THMS). T1 Mode
Bit 7 : Transmit HDLC-256 Mode Select (THMS). E1 Mode
Bit 6 : Transmit HDLC-256 Enable (THEN).
Bit 2: Transmit BERT Port Direction Control (TBPDIR)
Bit 1: Transmit BERT Port Framed/Unframed Select (TBPFUS). T1 mode only
Bit 0: Transmit BERT Port Enable (TBPEN)
19-5856; Rev 4; 5/11
0 = Transmit HDLC-256 assigned to timeslots
1 = Transmit HDLC-256 assigned to FDL Bits
0 = Transmit HDLC-256 assigned to timeslots
1 = Transmit HDLC-256 assigned to the Sa Bits
0 = Transmit HDLC-256 is not active.
1 = Transmit HDLC-256 is active.
0 = Normal (line) operation. Transmit BERT port sources data into the transmit path.
1 = System (backplane) operation. Transmit BERT port sources data into the receive path (RSERn). In this
mode, the data from the BERT is muxed into the receive path.
0 = The DS26514’s transmit BERT will not clock data into the F-bit position (framed).
1 = The DS26514’s transmit BERT will clock data into the F-bit position (unframed).
0 = Transmit BERT port is not active.
1 = Transmit BERT port is active.
THMS
7
0
TXPC
Transmit Expansion Port Control Register
18Ah + (200h x (n - 1)) : where n = 1 to 4
THEN
6
0
—
5
0
—
4
0
—
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TBPDIR
2
0
TBPFUS
1
0
222 of 305
TBPEN
0
0
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