DS26514G Maxim Integrated, DS26514G Datasheet - Page 258

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

emptied, any transfer in progress is halted, the FIFO RAM is powered down, and all incoming data is discarded (all
TFDR register writes are ignored).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Transmit HDLC Data Storage Available Level (TDAL[4:0]) – These five bits indicate the minimum
number of bytes ([TDAL*8]+1) that must be available for storage (do not contain data) in the Transmit FIFO for
HDLC data storage to be available. For example, a value of 21 (15h) results in HDLC data storage being available
(THDA = 1) when the Transmit FIFO has 169 (A9h) bytes or more available for storage, and HDLC data storage
not being available (THDA = 0) when the Transmit FIFO has 168 (A8h) bytes or less available for storage. Default
value (after reset) is 128 bytes minimum available.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Transmit FIFO Data Packet End (TDPE) – When 0, the Transmit FIFO data is not a packet end. When 1,
the Transmit FIFO data is a packet end. This bit should be written before the last byte of the packet is written into
TH256FDR2.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
When read, the value of these bits is always zero.
Bits 7 to 0: Transmit FIFO Data (TFD[7:0]) – These eight bits are the packet data to be stored in the Transmit
FIFO. TFD[7] is the MSB, and TFD[0] is the LSB. If bit reordering is disabled, TFD[0] is the first bit transmitted, and
TFD[7] is the last bit transmitted. If bit reordering is enabled, TFD[7] is the first bit transmitted, and TFD[0] is the
last bit transmitted.
19-5856; Rev 4; 5/11
TFD7
--
--
7
0
7
0
7
0
TFD6
--
--
6
0
6
0
6
0
TH256CR2
Transmit HDLC-256 Transmit Control Register 2
1501h + (20h x (n-1)) : where n = 1 to 4
TH256FDR1
Transmit HDLC-256 FIFO Data Register 1
1502h + (20h x (n-1)) : where n = 1 to 4
TH256FDR2
Transmit HDLC-256 FIFO Data Register 2
1503h + (20h x (n-1)) : where n = 1 to 4
TFD5
--
--
5
0
5
0
5
0
TDAL4
TFD4
--
4
0
4
0
4
0
TDAL3
TFD3
--
3
1
3
0
3
0
DS26514 4-Port T1/E1/J1 Transceiver
TDAL2
TFD2
--
2
0
2
0
2
0
TDAL1
TFD1
--
1
0
1
0
1
0
TDAL0
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TDPE
TFD0
0
0
0
0
0
0