DS26514G Maxim Integrated, DS26514G Datasheet - Page 77

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

9.10.2 Transmit HDLC-64 Controller
9.10.2.1
The Transmit HDLC FIFO Buffer Available Register (TFBA) indicates the number of bytes that can be written into
the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the
transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable
during the read cycle.
9.10.2.2
The HDLC status registers in the DS26514 allow for flexible software interface to meet the user’s preferences.
When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status
registers, or a combination of polling and interrupt processes can be used.
for using the DS26514 HDLC receiver.
19-5856; Rev 4; 5/11
FIFO Information
Transmit HDLC-64 Example
Figure 9-18
DS26514 4-Port T1/E1/J1 Transceiver
shows an example routine
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