DS26514G Maxim Integrated, DS26514G Datasheet - Page 261

• Manufacturer Part Number: DS26514G
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26514G

• Part # Aliases: 90-26514-G00

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Receive Bit Reordering Enable (RBRE) – When 0, bit reordering is disabled (The first bit received is in the
LSB of the Receive FIFO Data byte RFD[0]). When 1, bit reordering is enabled (The first bit received is in the MSB
of the Receive FIFO Data byte RFD[7]).
Bit 2: Receive Data Inversion Enable (RDIE) – When 0, the incoming data is directly passed on for packet
processing. When 1, the incoming data is inverted before being passed on for packet processing.
Bit 1: Receive FCS Processing Disable (RFPD) – When 0, FCS processing is performed (the packets have a
FCS appended). When 1, FCS processing is disabled (the packets do not have a FCS appended).
Bit 0: Receive FIFO Reset (RFRST) – When 0, the Receive FIFO will resume normal operations, however, data is
discarded until a start of packet is received after RAM power-up is completed. When 1, the Receive FIFO is
emptied, any transfer in progress is halted, the FIFO RAM is powered down, the RHDA bit is forced low, and all
incoming data is discarded.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Receive HDLC Data Available Level (RDAL[4:0]) – These five bits indicate the minimum number of
eight byte groups that must be stored (contain data) in the Receive FIFO before HDLC data is considered to be
available (RHDA=1). For example, a value of 21 (15h) results in HDLC data being available when the Receive
FIFO contains 168 (A8h) bytes or more.
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit 2: Receive FIFO Full (RFF) – When 0, the Receive FIFO contains 255 or less bytes of data. When 1, the
Receive FIFO is full.
Bit 1: Receive FIFO Empty (RFE) – When 0, the Receive FIFO contains at least one byte of data. When 1, the
Receive FIFO is empty.
Bit 0: Receive HDLC Data Available (RHDA) – When 0, the Receive FIFO contains less data than the Receive
HDLC data available level (RDAL[4:0]). When 1, the Receive FIFO contains the same or more data than the
Receive HDLC data available level.
19-5856; Rev 4; 5/11
--
--
--
7
0
7
0
7
--
--
--
6
0
6
0
6
RH256CR1
Receive HDLC-256 Control Register 1
1510 + (20h x (n-1)) : where n = 1 to 4
RH256CR2
Receive HDLC-256 Control Register 2
1511h+ (20h x (n-1)) : where n = 1 to 4
RH256SR
Receive HDLC-256 Status Register
1514h+ (20h x (n-1)) : where n = 1 to 4
--
--
--
5
0
5
0
5
RDAL4
--
--
4
0
4
0
4
RDAL3
RBRE
--
3
0
3
1
3
DS26514 4-Port T1/E1/J1 Transceiver
RDAL2
RDIE
RFF
2
0
2
0
2
RDAL1
RFPD
RFE
1
0
1
0
1
RFRST
RDAL0
261 of 305
RHDA
0
0
0
0
0