TDGL007 Microchip Technology, TDGL007 Datasheet - Page 194

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 17-1:
DS70594C-page 194
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10-8
bit 7
bit 6
bit 5
Note 1: When configured for QEI mode, the control bit is a ‘don’t care’.
CNTERR
SWPAB
R/W-0
R/W-0
CNTERR: Count Error Status Flag bit
1 = Position count error has occurred
0 = No position count error has occurred
(CNTERR flag only applies when QEIM<2:0> = ‘110’ or ‘100’)
Unimplemented: Read as ‘0’
QEISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
INDEX: Index Pin State Status bit (read-only)
1 = Index pin is High
0 = Index pin is Low
UPDN: Position Counter Direction Status bit
1 = Position counter direction is positive (+)
0 = Position counter direction is negative (-)
(Read-only bit when QEIM<2:0> = ‘1xx’. Read/write bit when QEIM<2:0> = 001.)
QEIM<2:0>: Quadrature Encoder Interface Mode Select bits
111 = Quadrature Encoder Interface enabled (x4 mode) with Position Counter Reset by match (MAXCNT)
110 = Quadrature Encoder Interface enabled (x4 mode) with Index Pulse Reset of position counter
101 = Quadrature Encoder Interface enabled (x2 mode) with Position Counter Reset by match (MAXCNT)
100 = Quadrature Encoder Interface enabled (x2 mode) with Index Pulse Reset of position counter
011 = Unused (module disabled)
010 = Unused (module disabled)
001 = Starts 16-bit Timer
000 = Quadrature Encoder Interface/timer off
SWPAB: Phase A and Phase B Input Swap Select bit
1 = Phase A and Phase B inputs swapped
0 = Phase A and Phase B inputs not swapped
PCDOUT: Position Counter Direction State Output Enable bit
1 = Position counter direction status output enable (QEI logic controls state of I/O pin)
0 = Position counter direction status output disabled (normal I/O pin operation)
TQGATE: Timer Gated Time Accumulation Enable bit
1 = Timer gated time accumulation enabled
0 = Timer gated time accumulation disabled
PCDOUT
R/W-0
U-0
—
QEIxCON: QEIx CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
QEISIDL
TQGATE
R/W-0
R/W-0
INDEX
R/W-0
R-0
TQCKPS<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
UPDN
R/W-0
POSRES
R/W-0
R/W-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
QEIM<2:0>
R/W-0
R/W-0
TQCS
UPDN_SRC
R/W-0
R/W-0
bit 8
bit 0
(1)