TDGL007 Microchip Technology, TDGL007 Datasheet - Page 81

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

6.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode and Uninitialized W
FIGURE 6-1:
© 2011 Microchip Technology Inc.
Register Reset
Note 1: This data sheet summarizes the fea-
2: Some registers and associated bits
RESET
tures of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. How-
ever, it is not intended to be a compre-
hensive
complement the information in this
data
“Reset” (DS70192) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
MCLR
V
DD
sheet,
Uninitialized W Register
RESET SYSTEM BLOCK DIAGRAM
reference
dsPIC33FJXXXMCX06A/X08A/X10A
RESET Instruction
Regulator
Internal
Sleep or Idle
refer
Module
Illegal Opcode
WDT
Trap Conflict
to
source.
V
Section
Detect
DD
Glitch Filter
Rise
To
BOR
POR
8.
in
A simplified block diagram of the Reset module is
shown in
Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see
the POR bit (RCON<0>), which is set. The user can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Register
Figure
Refer to the specific peripheral or CPU
section of this data sheet for register
Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
6-1). A POR will clear all bits except for
6-1.
SYSRST
DS70594C-page 81