TDGL007 Microchip Technology, TDGL007 Datasheet - Page 263

• Manufacturer Part Number: TDGL007
• Description: Development Boards & Kits - PIC / DSPIC DIGILENT CEREBOT MC7 MOTOR CONTROL BRD
• Manufacturer: Microchip Technology

Specifications of TDGL007

• Product: Development Boards
• Interface Type: CAN, I2C
• Operating Supply Voltage: 5 V

23.4
For dsPIC33FJXXXMCX06A/X08A/X10A devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>) which allow the selec-
tion of a total of 16 settings, from 1:1 to 1:32,768. Using
the prescaler and postscaler, time-out periods ranging
from 1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
FIGURE 23-2:
© 2011 Microchip Technology Inc.
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
Watchdog Timer (WDT)
WINDIS
WDT BLOCK DIAGRAM
WDT
dsPIC33FJXXXMCX06A/X08A/X10A
) of 1 ms in 5-bit mode, or
(divide by N1)
WDTPRE
Prescaler
RS
WDT Window Select
Watchdog Timer
If the WDT is enabled, it will continue to run during Sleep
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will con-
tinue from where the PWRSAV instruction was executed.
The corresponding SLEEP or IDLE bits (RCON<3,2>) will
need to be cleared in software after the device wakes up.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed to
‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN control
bit is cleared on any device Reset. The software WDT
option allows the user to enable the WDT for critical
code segments and disable the WDT during non-critical
segments for maximum power savings.
RS
WDTPOST<3:0>
(divide by N2)
Note:
Note:
Postscaler
CLRWDT Instruction
window can be determined by using a timer.
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
If the WINDIS bit (FWDT<6>) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
Sleep/Idle
1
0
DS70594C-page 263
WDT
Wake-up
WDT
Reset