N25Q128A13BSF40F NUMONYX, N25Q128A13BSF40F Datasheet - Page 25

• Manufacturer Part Number: N25Q128A13BSF40F
• Description: IC SRL FLASH 128MB NMX 16-SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BSF40F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
5.1.9
5.1.10
Active power and standby power modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the active power
mode until all internal cycles have completed (program, erase, write status register, Write
Non Volatile Configuration Register). The device then goes in to the standby power mode.
The device consumption drops to I
Hold (or Reset) condition
The Hold (HOLD) signal is used to pause serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
write status register, Write Non Volatile Configuration Register, program, or erase cycle that
is currently in progress.
To enter the hold condition, the device must be selected, with Chip Select (S) Low.
The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that the
Serial Clock (C) is Low (as shown in
The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that the
Serial Clock (C) is Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes
Low (this is shown in
During the hold condition, the serial data output (DQ1) is high impedance, and serial data
input (DQ0) and Serial Clock (C) are don’t care.
Normally, the device is kept selected, with Chip Select (S) driven Low for the whole duration
of the hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the hold condition.
Figure 7.
Reset functionality is available instead of Hold in parts with a dedicated part number. See
Section 16: Ordering
HOLD
C
Hold condition activation
information.
Figure
7).
(standard use)
condition
Hold
CC1
Figure
.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7).
(non-standard use)
©2010 Micron Technology, Inc. All rights reserved.
condition
Hold
Operating features
AI02029D
25/157