N25Q128A13BSF40F NUMONYX, N25Q128A13BSF40F Datasheet - Page 80

• Manufacturer Part Number: N25Q128A13BSF40F
• Description: IC SRL FLASH 128MB NMX 16-SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BSF40F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
80/157
Figure 32. Write Status Register instruction sequence
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W/VPP) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two
cases need to be considered, depending on the state of Write Protect (W/VPP):
Regardless of the order of the two events, the Hardware Protected mode (HPM) can be
entered in either of the following ways:
The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write
Protect (W/VPP) High.
If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can
never be activated, and only the Software Protected mode (SPM2) using the Block Protect
(BP3, BP2, BP1, BP0) bits and the Top/Bottom (T/B) bit of the Status Register can be used.
S
C
DQ0
DQ1
If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register
even if the Write Enable Latch (WEL) bit has been set previously by a Write Enable
(WREN) instruction. Therefore, all data bytes in the memory area that are software
protected (SPM2) by the Block Protect (BP3, BP2, BP1, BP0) bits and the Top/Bottom
(T/B) bit of the Status Register are also hardware protected against data modification.
setting the Status Register Write Disable (SRWD) bit after driving Write Protect
(W/VPP) Low
driving Write Protect (W/VPP) Low after setting the Status Register Write Disable
(SRWD) bit.
0
1
High Impedance
2
Instruction
3
4
5
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
MSB
7
8
6
9 10 11 12 13 14 15
5
register in
4
Status
3
2
1
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N25Q128 - 3 V