N25Q128A13BSF40F NUMONYX, N25Q128A13BSF40F Datasheet - Page 88

• Manufacturer Part Number: N25Q128A13BSF40F
• Description: IC SRL FLASH 128MB NMX 16-SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BSF40F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
9.1.34
9.1.35
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S
C
DQ0
DQ1
Write Volatile Enhanced Configuration Register
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new
values to be written to the Volatile Enhanced Configuration register. Before it can be
accepted, a write enable (WREN) instruction must previously have been executed. After the
write enable (WREN) instruction has been decoded and executed, the device sets the write
enable latch (WEL).
The Write Volatile Enhanced Configuration register (WRVECR) instruction is entered by
driving Chip Select (S) Low, followed by the instruction code and the data byte on serial data
input (DQ0).
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Volatile Enhanced Configuration register (WRVECR) instruction is not
executed. When the new data are latched, the write enable latch (WEL) is reset.
The Write Volatile Enhanced Configuration register (WRVECR) instruction allows the user to
change the values of all the Volatile Enhanced Configuration Register bits.
The Write Volatile Enhanced Configuration Register impacts the memory behavior right after
the instruction is received by the device.
Figure 42. Write Volatile Enhanced Configuration Register instruction sequence
Reset Enable
The Reset operation is used as a system software reset that puts the device in the power-on
reset condition. All the lock bits, volatile configuration registers, and the extended address
register are reset to the power-on reset default condition after the reset software sequence
has been accepted. The power-on reset condition depends on non volatile configuration
register content. This Reset operation consists of two instructions: Reset Enable and Reset
Memory.
The Reset operation requires the Reset Enable instruction followed by the Reset Memory
instruction. If the Reset Enable instruction is followed by any instruction other than Reset
Memory, it is disabled. Reset Memory is also disabled if the device is selected by driving
chip select (S) and Clock (C) low.
0
1
High Impedance
2
Instruction
3
4
5
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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MSB
7
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6
9 10 11 12 13 14 15
5
VECR In
4
3
2
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N25Q128 - 3 V