N25Q128A13BSF40F NUMONYX, N25Q128A13BSF40F Datasheet - Page 61
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N25Q128A13BSF40F
Manufacturer Part Number
N25Q128A13BSF40F
Description
IC SRL FLASH 128MB NMX 16-SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.N25Q128A13B1240F.pdf
(157 pages)
Specifications of N25Q128A13BSF40F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A13BSF40F
Manufacturer:
MICRON
Quantity:
15 000
Part Number:
N25Q128A13BSF40F
Manufacturer:
MICRON
Quantity:
20 000
N25Q128 - 3 V
9.1.5
DQ0
DQ1
S
C
DQ0
DQ1
S
C
The Read SFDP instruction is terminated by driving Chip Select (S) High at any time during
data output.
Any Read Serial Flash Discovery Parameter (RDSFDP) instruction issued while an Erase or
Program cycle is in progress, is rejected without having any effect on the cycle that is in
progress.
Figure 13. Read Serial Flash Discovery Instruction and Data-out Sequence
*Address bits A<23:11> are “Don’t care.
Dual Output Fast Read (DOFR)
The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at
Higher Speed (FAST_READ) instruction, except that the data are shifted out on two pins
(pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one
doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed
(FAST_READ) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable
number of dummy clock cycles, each bit being latched-in during the rising edge of Serial
Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a
maximum frequency Fc, during the falling edge of Serial Clock (C).
0
7
32 33 34
1
6
High Impedance
Dummy cycles
2
5
Instruction
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
2
5
1
6
0
7
MSB
23
7
8
22 21
9 10
6
24-bit address*
5
DATA OUT 1
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
28 29 30 31
3
2
2
1
1
0
0
47
MSB
7
6
5
DATA OUT 2
4
©2010 Micron Technology, Inc. All rights reserved.
3
2
1
0
MSB
7
Instructions
61/157