PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 15

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
Table 1.
name
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Pin
Pin
Pin description (continued)
58
57
56
55
54
53
52
51
68
67
66
65
64
63
62
61
48
47
46
45
44
43
42
41
79
80
1
I/O CMOS
I/O CMOS
I/O CMOS
I/O CMOS
I/O CMOS
I/O CMOS
or Open
or Open
or Open
or Open
or Open
or Open
Drain
Drain
Drain
Drain
Drain
Drain
Type
These pins make up port A. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellA0-7) outputs.
Inputs to the PLDs.
Latched, transparent or registered PLD input.
These pins make up port B. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
CPLD macrocell (McellB0-7) output.
Inputs to the PLDs.
Latched, transparent or registered PLD input.
These pins make up port C. These port pins are configurable and can have the
following functions:
MCU I/O – write to or read from a standard output or input port.
External Chip Select (ECS0-7) output.
Latched, transparent or registered PLD input.
PD0 pin of port D. This port pin can be configured to have the following functions:
ALE/AS input latches addresses on ADIO0-ADIO15 pins.
AS input latches addresses on ADIO0-ADIO15 pins on the rising edge.
Input to the PLDs.
Transparent PLD input.
PD1 pin of port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Input to the PLDs.
CLKIN – clock input to the CPLD macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
PD2 pin of port D. This port pin can be configured to have the following functions:
MCU I/O – write to or read from a standard output or input port.
Input to the PLDs.
PSD Chip Select Input (CSI). When low, the MCU can access the PSD memory
and I/O. When high, the PSD memory blocks are disabled to conserve power. The
trailing edge of CSI can be used to get the PSD out of power-down mode.
Description
Description
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