PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 51

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
13
Page register
The 8-bit Page register increases the addressing capability of the MCU by a factor of up to
256. The contents of the register can also be read by the MCU. The outputs of the Page
register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector
Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the CPLD for general logic. See application note
AN1154.
Figure 11
internal data bus D0-D7. The MCU can write to or read from the Page register. The Page
register can be accessed at address location CSIOP + E0h.
Figure 11. Page register
shows the Page register. The eight flip-flops in the register are connected to the
RESET
D 0 - D 7
R/W
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
REGISTER
PAGE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
DPLD
CPLD
AND
PLD
INTERNAL
SELECTS
AND LOGIC
Page register
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