PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 59

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
15.4
Output macrocell (OMC)
Eight of the output macrocells (OMC) are connected to port A pins and are named as
McellA0-McellA7. The other eight macrocells are connected to port B pins and are named
as McellB0-McellB7.
The output macrocell (OMC) architecture is shown in
there are native product terms available from the AND Array, and borrowed product terms
available (if unused) from other output macrocells (OMC). The polarity of the product term is
controlled by the XOR gate. The output macrocell (OMC) can implement either sequential
logic, using the flip-flop element, or combinatorial logic.
The multiplexer selects between the sequential or combinatorial logic outputs. The
multiplexer output can drive a port pin and has a feedback path to the AND Array inputs.
The flip-flop in the output macrocell (OMC) block can be configured as a D, T, JK, or SR type
in the PSDsoft program. The flip-flop’s clock, preset, and clear inputs may be driven from a
product term of the AND Array. Alternatively, CLKIN (PD1) can be used for the clock input to
the flip-flop. The flip-flop is clocked to the rising edge of CLKIN (PD1). The preset and clear
are active high inputs. Each clear input can use up to two product terms.
Table 10.
macrocell
McellA0
McellA1
McellA2
McellA3
McellA4
McellA5
McellA6
McellA7
McellB0
McellB1
McellB2
McellB3
McellB4
McellB5
McellB6
McellB7
Output
Output macrocell port and data bit assignments
assignment
Port A0
Port A1
Port A2
Port A3
Port A4
Port A5
Port A6
Port A7
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
Port
Native product
terms
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
borrowed product
Figure
Maximum
terms
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
15. As shown in the figure,
Data bit for loading
or reading
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
59/120
PLDs