PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 75

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
17
17.1
I/O ports
There are seven programmable I/O ports: ports A, B, C, D, E and F. Each of the ports is
eight bits except for port D, which is 4 bits. Each port pin is individually user-configurable,
thus allowing multiple functions per port. The ports are configured using PSDsoft or by the
MCU writing to on-chip registers in the CSIOP space.
The topics discussed in this section are:
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General port architecture
The general architecture of the I/O port block is shown in
architectures are shown in
purpose for a port pin has been defined, that pin is no longer available for other purposes.
Exceptions are noted.
As shown in
driven by the configuration bits in the Control registers (Ports E, F and G only) and PSDsoft
Configuration. Inputs to the multiplexer include the following:
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The port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and
can be read by the MCU. The Data Out and macrocell outputs, Direction and Control
registers, and port pin input are all connected to the port Data Buffer (PDB).
The port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND Array enable product term and the Direction register. If the
enable product term of any of the Array outputs is not defined and that port pin is not defined
as a CPLD output in the PSDabel file, then the Direction register has sole control of the
buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The port Data Buffer (PDB)
feedback path allows the MCU to check the contents of the registers.
Ports A, B, and C have embedded input macrocells (IMC). The input macrocells (IMC) can
be configured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array.
The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the
MCU. See
General port architecture
Port operating modes
Port configuration registers (PCR)
Port data registers
Individual port functionality.
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS0-ECS2) from the CPLD.
Section 15.9: Input macrocells
Figure
25, the ports contain an output multiplexer whose select signals are
Figure
27,
Figure
(IMC).
28, and
Figure
Figure
29. In general, once the
25. Individual port
I/O ports
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