PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 96

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

Programming in-circuit using the JTAG/ISP interface
20.2
20.3
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JTAG extensions
TSTAT and TERR are two JTAG extension signals enabled by an JTAG command received
over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed
Program and Erase cycles by indicating status on PSD signals instead of having to scan the
status out serially using the standard JTAG channel. See Application Note AN1153.
TERR indicates if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal goes low (active) when an Error condition occurs, and stays low
until a special JTAG command is executed or a chip Reset (RESET) pulse is received after
an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy described in the section entitled
Ready/Busy
secondary Flash memory contents can be read). TSTAT is low when Flash memory
Program or Erase cycles are in progress, and also when data is being written to the
secondary Flash memory.
TSTAT and TERR can be configured as open-drain type signals during a JTAG command.
Security and Flash memory protection
When the Security bit is set, the device cannot be read on a Device Programmer or through
the JTAG port. When using the JTAG port, only a Full Chip Erase command is allowed.
All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the part
to a non-secured blank state. The Security bit can be set in PSDsoft.
All primary and secondary Flash memory sectors can individually be sector protected
against erasures. The Sector Protect bits can be set in PSDsoft.
Table 27.
PE0
PE1
PE2
PE3
PE4
PE5
Port E pin
(PE4). TSTAT is high when the PSD device is in READ mode (primary and
JTAG port signals
TMS
TCK
TDI
TDO
TSTAT
TERR
JTAG signals
Clock
Serial Data In
Serial Data Out
Status
Mode Select
Error flag
Description
Section 6.5:
PSD835G2