PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 92

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PSD835G2-90U

Manufacturer Part Number
PSD835G2-90U
Description
IC FLASH 4MBIT 90NS 80TQFP
Manufacturer
STMicroelectronics
Datasheet

Specifications of PSD835G2-90U

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
90ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-2015

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0
Power management
18.6
92/120
Input control signals
The PSD provides the option to turn off the address input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/AS, PD0) and DBE) to the PLD to save AC
power consumption. These signals are inputs to the PLD AND Array. During Power-down
mode, or, if any of them are not being used as part of the PLD logic equation, these signals
should be disabled to save AC power. They are disconnected from the PLD AND Array by
setting bits 0, 2, 3, 4, 5, and 6 to a ‘1’ in PMMR2.
Table 25.
APD Enable
bit
0
1
1
1
APD counter operation
ALE PD
Polarity
X
X
1
0
ALE Level
Pulsing
X
1
0
Not counting
Not counting
Counting (generates PDN after 15 clock cycles)
Counting (generates PDN after 15 clock cycles)
APD counter
PSD835G2

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