PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 81

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
17.13
direction register, but also by the output enable product term from the PLD AND Array. If the
output enable product term is not active, the Direction register has sole control of a given
pin’s direction.
An example of a configuration for a port with the three least significant bits set to output and
the remainder set to input is shown in
in
Drive Select register
The Drive Select register configures the pin driver as Open Drain or CMOS for some port
pins, and controls the slew rate for the other port pins. An external pull-up resistor should be
used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corresponding bit in the Drive Select register is
set to a '1.' The default pin drive is CMOS.
Note that the slew rate is a measurement of the rise and fall times of an output. A higher
slew rate means a faster output response and may create more electrical noise. A pin
operates at a high slew rate when the corresponding bit in the Drive register is set to '1.' The
default rate is slow slew.
Table 21
be configured as Open Drain outputs and which pins the slew rate can be set for.
Table 17.
1. See
Table 18.
Table 19.
Control
Direction
Drive Select
Figure
Direction register bit
Table 21
Register name
shows the Drive register for ports A, B, C, D, E and F. It summarizes which pins can
28), the Direction register for port D has only the four least significant bits active.
(1)
Port configuration registers (PCR)
Port Pin Direction Control, Output Enable P.T. not defined
Direction register bit
Port Pin Direction Control, Output Enable P.T. Defined
for Drive register bit definition.
0
0
1
1
0
1
E, F, G
A,B,C,D, E, F, G
A,B,C,D, E, F, G
Output Enable P.T.
Table
Port
20. Since port D only contains four pins (shown
0
1
0
1
Port Pin mode
WRITE/READ
WRITE/READ
WRITE/READ
Output
Input
Port Pin mode
MCU access
Output
Output
Output
Input
I/O ports
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