PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 77

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
17.3
17.4
17.5
MCU I/O mode
In the MCU I/O mode, the MCU uses the I/O ports block to expand its own I/O ports. By
setting up the CSIOP space, the ports on the PSD are mapped into the MCU address
space. The addresses of the ports are listed in
A port pin can be put into MCU I/O mode by writing a ’0’ to the corresponding bit in the
Control register (Ports E, F and G). The MCU I/O direction may be changed by writing to the
corresponding bit in the Direction register, or by the output enable product term. See
Section 17.12: Direction register on page
content of the Data Out register drives the pin. When configured as an input, the MCU can
read the port input through the Data In buffer (see
Ports A, B and C do not have Control registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if they are specified in PSDsoft.
PLD I/O mode
The PLD I/O mode uses a port as an input to the CPLD’s input macrocells (IMC), and/or as
an output from the CPLD’s output macrocells (OMC). The output can be tri-stated with a
control signal. This output enable control signal can be defined by a product term from the
PLD, or by resetting the corresponding bit in the Direction register to '0.' The corresponding
bit in the Direction register must not be set to ’1’ if the pin is defined as a PLD input pin in
PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then
specifying an equation in PSDsoft.
Address Out mode
For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive
latched addresses on to the port pins. These port pins can, in turn, drive external devices.
Either the output enable or the corresponding bits of both the Direction register and Control
register must be set to a ’1’ for pins to use Address Out mode. This must be done by the
MCU at run-time. See
for various MCUs.
Note: Do not drive address signals with Address Out mode to an external memory device if
it is intended for the MCU to Boot from the external device. The MCU must first Boot from
PSD memory so the Direction and Control register bits can be set.
Table 14.
MCU I/O
PLD I/O
McellA outputs
McellB outputs
Additional Ext. CS
outputs
PLD inputs
Port mode
Port operating modes
Table 16
Port A
Yes
Yes
Yes
No
No
for the address output pin assignments on ports E, F and G
Port B
Yes
Yes
Yes
No
No
80. When the pin is configured as an output, the
Port C
Yes
Yes
Yes
No
No
Table
Figure
Port D
Yes
Yes
No
No
No
5.
25).
Port E
Yes
No
No
No
No
Port F
Yes
Yes
Yes
No
No
I/O ports
Port G
Yes
No
No
No
No
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