PSD835G2-90U STMicroelectronics, PSD835G2-90U Datasheet - Page 95

• Manufacturer Part Number: PSD835G2-90U
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD835G2-90U

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2015

PSD835G2
20
20.1
Programming in-circuit using the JTAG/ISP interface
The JTAG/ISP Interface block can be enabled on port E (see
(primary and secondary Flash memory), PLD logic, and PSD Configuration register bits may
be programmed through the JTAG/ISP Interface block. A blank device can be mounted on a
printed circuit board and programmed using JTAG/ISP.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up Program and
Erase cycles.
By default, on a blank PSD (as shipped from the factory or after erasure), four pins on port E
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Application Note AN1153 for more details on JTAG In-System Programming (ISP).
Standard JTAG signals
The standard JTAG signals (TMS, TCK, TDI, and TDO) can be enabled by any of three
different conditions that are logically ORed. When enabled, TDI, TDO, TCK, and TMS are
inputs, waiting for a JTAG serial command from an external JTAG controller device (such as
FlashLINK or Automated Test Equipment). When the enabling command is received, TDO
becomes an output and the JTAG channel is fully functional inside the PSD. The same
command that enables the JTAG channel may optionally enable the two additional JTAG
signals, TSTAT and TERR.
The following symbolic logic equation specifies the conditions enabling the four basic JTAG
signals (TMS, TCK, TDI, and TDO) on their respective port E pins. For purposes of
discussion, the logic label JTAG_ON is used. When JTAG_ON is true, the four pins are
enabled for JTAG. When JTAG_ON is false, the four pins can be used for general PSD I/O.
JTAG_ON = PSDsoft_enabled +
in the PSDsoft Configuration utility. This dedicates the pins for
JTAG at all times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
PSD register, JTAG Enable. This register is located at address CSIOP
+ offset C7h. Setting the JTAG_ENABLE bit in this register will
enable the pins for JTAG use. This bit is cleared by a PSD reset or
the microcontroller. See
definition. */
PSD_product_term_enabled;
enable the JTAG pins. This PT has the reserved name JTAGSEL. Once
defined as a node in PSDabel, the designer can write an equation for
JTAGSEL. This method is used when the port E JTAG pins are
multiplexed with other I/O signals. It is recommended to logically
tie the node JTAGSEL to the JEN\ signal on the Flashlink cable when
multiplexing JTAG signals. See Application Note 1153 for details. */
The PSD supports JTAG/ISP commands, but not Boundary Scan. The PSDsoft software
tool and FlashLINK JTAG programming cable implement the JTAG/ISP commands.
/* An NVM configuration bit inside the PSD is set by the designer
/* The microcontroller can set a bit at run-time by writing to the
/* A dedicated product term (PT) inside the PSD can be used to
Section : JTAG Enable register
Programming in-circuit using the JTAG/ISP interface
Table
27). All memory blocks
for bit
95/120