XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 11

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Bus Operations
There are six standard bus operations that control the
device: Bus Read, Bus Write, Address Latch, Output
Disable, Standby and Reset
Bus Read
Bus Read operations are used to output the contents of the
Memory Array, Electronic Signature, Status Register and
Common Flash Interface. Both Chip Enable and Output
Enable must be at V
The Chip Enable input should be used to enable the device.
Output Enable should be used to gate data onto the output.
The data read depends on the previous command written to
the memory (see
Bus Write
Bus Write operations write commands to the memory or
latch Input Data to be programmed. A Bus Write operation
is initiated when Chip Enable and Write Enable are at V
with Output Enable at V
Addresses are latched on the rising edge of Write Enable or
Chip Enable, whichever occurs first. The addresses can be
latched prior to the write operation by toggling Latch Enable
(when Chip Enable is at V
The Latch Enable signal can also be held at V
system, but then the system must guarantee that the
address lines remain stable for at least T
Note:
Write Enable are ignored by the memory and do not affect Bus
Write operations.
Table 5: Bus Operations
DS617 (v3.0.1) January 07, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
7.
Output Disable
Address Latch
Operation
Bus Read
Bus Write
X = Don't care.
If READY_WAIT is configured as an output wait signal (CR4 = 0), then the CR10 Configuration Register bit defines the signal polarity.
READY_WAIT is configured using the CR4 Configuration Register bit.
L can be tied to V
Depends on G.
The Configuration Register reverts to its default value after a Low logic level (V
READY_WAIT pin used as an output. READY_WAIT goes Low T
Standby
Reset
FALS
Typically glitches of less than 5 ns on Chip Enable or
R
“Command
IH
V
V
V
V
V
V
IL
E
X
IH
IL
IL
IL
IL
IL
if the valid address was previously latched.
in order to perform a read operation.
IH
. Commands, Input Data and
IL
(1)
V
V
V
V
G
X
X
X
).
IH
IH
IL
IL
(Table
Interface,”
V
V
V
V
V
W
X
X
IH
IH
IH
IH
IL
5).
V
V
V
V
IL
IL
X
X
X
L
IH
page
IL
(4)
(4)
WHAX
V
14).
RP
V
V
V
V
V
V
IL
.
IL
IH
IH
IH
IH
IH
IH
(6)
by the
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
IL
CR4 = 1
PLRWL
V
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IL
(7)
Address Latch
Address latch operations input valid addresses. Both Chip
enable and Latch Enable must be at V
latch operations. Addresses are latched on the rising edge
of Latch Enable.
Output Disable
The outputs are held at high impedance when Output
Enable is at V
Standby
Standby disables most of the internal circuitry allowing a
substantial reduction of the current consumption. The
memory is in standby when Chip Enable and Reset are at
V
I
independently from Output Enable or Write Enable. If Chip
Enable switches to V
the device enters Standby mode when finished with the
program or erase operation.
Reset
During Reset mode, the memory is deselected and the
outputs are high impedance. The memory is in Reset mode
when Reset is at V
Reset level independently from Chip Enable, Output Enable
or Write Enable. If Reset is pulled to V
or Erase, this operation is aborted and the memory content
is no longer valid.
DD3
IH
after RP goes Low.
READY_WAIT
. Power consumption is reduced to the standby level
, and the outputs are set to high impedance
IL
) is detected on the RP pin.
IH
.
(2,3)
IL
CR4 = 0
IH
. Power consumption is reduced to the
Hi-Z
Hi-Z
–
–
during a program or erase operation,
–
–
–
Data output or Hi-Z
SS
IL
during address
during a Program
DQ15-DQ0
Data output
Data output
Data input
Hi-Z
Hi-Z
Hi-Z
(5)
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