XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 24

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Configuration Register
The Configuration Register is used to configure the type of bus access that the memory performs. Refer to
page 34
The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a
reset or power-up, the device is configured for Synchronous Read (CR15 = 0). The Configuration Register bits
page
and
Table 12: Configuration Register Bits
DS617 (v3.0.1) January 07, 2010
Product Specification
Notes:
1.
2.
Figure 10, page 30
CR13–CR11
The combination X-Latency = 2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
CR3 (wrap/no wrap) bit has no effect when CR2-CR0 (burst length) bits are set to continuous burst mode. Platform Flash XL wraps to the first
memory address after the device outputs the data from the last memory address.
CR2–CR0
26) specify the selection of the burst length, burst type, burst X latency, and read operation. Refer to
CR3
CR15
CR14
CR10
CR9
CR8
CR7
CR6
CR5
CR4
Bits
for details on read operations.
(2)
R
(2)
Wait Configuration
Valid Clock Edge
for examples of synchronous burst configurations.
Clock Latency
Device_ready
Description
configuration
Burst Length
Wait Polarity
Read mode
Data output
Wrap burst
Burst Type
Reserved
Reserved
Other configurations reserved
Value
010
011
100
101
110
111
001
010
011
111
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
Synchronous Read (default)
Asynchronous Read
2 clock latency
3 clock latency
4 clock latency
5 clock latency
6 clock latency
7 clock latency (default)
READY_WAIT with Wait function (CR4 = 0) is active Low
READY_WAIT with Wait function (CR4 = 0) is active High (default)
Data held for 1 clock cycle (default)
Data held for 2 clock cycles
Wait active during wait state
Wait active 1 clock cycle before wait state (default)
Reserved
Sequential (default)
Falling clock edge
Rising clock edge (default)
READY_WAIT signal has the Wait function
READY_WAIT signal has the Ready function (default)
Wrap
No wrap (default)
4 words
8 words
16 words
Continuous (default)
–
(1)
Description
(1)
Figure 9, page 28
"Read Modes,"
(Table 12,
24