XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 2

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

X-Ref Target - Figure 1
Notes:
1.
Platform Flash XL support is integrated with the Xilinx
design and debug tool suite.The iMPACT application,
included with the ISE software, supports indirect, in-system
programming of Platform Flash XL via the IEEE Standard
1149.1 (JTAG) port on the FPGA for prototype programming
(Figure
X-Ref Target - Figure 3
DS617 (v3.0.1) January 07, 2010
Product Specification
System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the
maximum configuration clock frequency, check the minimum clock period (T
to-output valid time (T
3).
R
Figure 1: Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration
KHQV
Direct FPGA Configuration/Debug and
Platform Flash XL
), and the FPGA SelectMAP setup time.
Figure 3: Indirect Programming Solution for Platform Flash XL
FPGA Design
(.bit) File
Single Cable Connector for
Indirect Platform Flash XL
READY_WAIT
Platform Flash XL
FPGA Design
(.bit) File
Programming
Cable Connector
Xilinx JTAG
Platform Flash XL High-Density Configuration and Storage Device
Wide (16-bit) Datapath
Clock up to 50 MHz
Synchronization
www.xilinx.com
Up to 800 Mb/s
Configuration
Data/Commands
Handshake
Address
Control
X-Ref Target - Figure 2
Platform Flash XL
Figure 2: Standard NOR Flash Interface for User
(1)
KHKH
Design (.bit)
Design (.bit)
File, Rev. 1
File, Rev. 0
User Data
Code
) for the chosen I/O voltage range (V
FPGA
Platform Flash XL
Platform Flash XL
For Programming
For Programming
Access to Memory
Programming
FPGA
In-System
Indirect,
Engine
Data/Commands
DS617_03_081209
DS617_01_102709
Address
Control
DDQ
), the clock High-
User Design
FPGA
DS617_02_081209
2