XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 66

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Table 41: Protection Register Information
Table 42: Burst Read Information
Table 43: Bank and Erase Block Region Information
DS617 (v3.0.1) January 07, 2010
Product Specification
Notes:
1.
2.
The variable P is a pointer which is defined at CFI offset 015h.
Bank Regions. There are two Bank Regions, see
(P+ 11)h = 11Bh
(P+1A)h = 124h
(P+1B)h = 125h
(P+1C)h = 126h
(P+1D)h = 127h
(P+1E)h = 128h
(P+1F)h = 129h
(P+10)h = 11Ah
(P+12)h = 11Ch
(P+13)h = 11Dh
(P+14)h = 11Eh
(P+15)h = 11Fh
(P+16)h = 120h
(P+17)h = 121h
(P+18)h = 122h
(P+19)h = 123h
(P+20)h = 12Ah
(P+22)h = 12Ch
(P+23)h = 12Dh
(P-21)h = 12Bh
(P+E)h = 118h
(P+F)h = 119h
Offset
Offset
Offset
R
0002h
0080h
0000h
0003h
0003h
0089h
0000h
0000h
0000h
0000h
0000h
0000h
0010h
0000h
0004h
0003h
0004h
0001h
0002h
0003h
0007h
Data
Data
Data
02h
Number of protection register fields in JEDEC ID space. 0000h indicates that
256 fields are available.
Protection Register 1: Protection Description:
Protection Register 2: Protection Description:
Page-mode read capability
Number of synchronous mode read configuration fields that follow.
Synchronous mode read capability configuration 1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
Number of Bank Regions within the device
Bits 0-7 Lower byte of protection register address
Bits 8-15 Upper byte of protection register address
Bits 16-23 2
Bits 24-31 2
Bits 0-31 protection register address
Bits 32-39
Bits 40-47
Bits 48-55 2
Bits 56-63
Bits 64-71
Bits 72-79 2n bytes in user programmable region
bits 0-7 n’ such that 2
bytes. See offset 0028h for device word width to determine page-mode data
output width.
bit 3-7 Reserved
bit 0-2 n’ such that 2
continuous synchronous reads when the device is configured for its
maximum word width. A value of 07h indicates that the device is capable of
continuous linear bursts that output data until the internal burst counter
reaches the end of the device’s burstable address space. This field’s 3-bit
value can be written directly to the read configuration register bit 0-2 if the
device is configured for its maximum word width. See offset 0028h for word
width to determine the burst data output width.
Table 35, page
n
n
n
n
Platform Flash XL High-Density Configuration and Storage Device
n
n
n
number of factory programmed regions (lower byte)
number of factory programmed regions (upper byte)
number of user programmable regions (lower byte)
number of user programmable regions (upper byte)
bytes in factory pre-programmed region
bytes in user programmable region
bytes in factory programmable region
www.xilinx.com
(1,2)
n+1
61.
n
HEX value represents the number of read-page
HEX value represents the maximum number of
Description
Description
Description
8 bytes
8 bytes
8 bytes
Value
Value
Cont.
80h
00h
89h
00h
00h
00h
16
16
16
2
0
0
0
0
4
4
8
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