XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 15

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Buffer Enhanced Factory Program Command
The Buffer Enhanced Factory Program command has been
specially developed to speed up programming in
manufacturing environments where the programming time
is critical. The command is used to program one or more
Write Buffer(s) of 32 words to a block. After the device
enters Buffer Enhanced Factory Program mode, the Write
Buffer can be reloaded any number of times as long as the
address remains within the same block. Only one block can
be programmed at a time.
If the block being programmed is protected, then the
Program operation aborts, data in the block is not changed,
and the Status Register outputs the error.
The use of the Buffer Enhanced Factory Program command
requires certain operating conditions:
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•
•
•
•
•
Dual operations are not supported during the Buffer
Enhanced Factory Program operation, and the command
cannot be suspended.
The Buffer Enhanced Factory Program Command consists
of three phases: Setup, Program and Verify, and Exit (refer
to
Setup Phase
The Buffer Enhanced Factory Program command requires
two Bus Write cycles to initiate the command:
•
•
After the confirm command is issued, read operations
output the contents of the Status Register.
The Status Register Program/Erase Controller (P/E.C). Bit
SR7 should be read to check that the P/E.C. is ready to
proceed to the next phase.
If an error is detected, SR4 goes High (set to ‘1’) and the
Buffer Enhanced Factory Program operation is terminated.
See
Program and Verify Phase
The Program and Verify Phase requires 32 cycles to program
the 32 words to the Write Buffer. Data is stored sequentially,
starting at the first address of the Write Buffer until the Write
DS617 (v3.0.1) January 07, 2010
Product Specification
Table 8, page 21
V
V
Ambient temperature T
The targeted block must be unlocked.
The start address must be aligned with the start of a
32- word buffer boundary.
The address must remain the Start Address
throughout programming.
The first Bus Write cycle sets up the Buffer Enhanced
Factory Program command.
The second Bus Write cycle confirms the command.
Caution!
issued as it is interpreted as data to program.
"Status Register," page 23
PP
DD
must be set to V
must be within operating range.
R
The read Status Register command must not be
for detail information).
PPH
A
.
must be 30°C ±10°C.
for details on the error.
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
Buffer is full (32 words). To program less than 32 words, the
remaining words should be programmed with FFFFh.
Four successive steps are required to issue and execute the
Program and Verify Phase of the command.
1. One Bus Write operation is used to latch the Start
2. Each subsequent word to be programmed is latched
3. After the Write Buffer is full, the data is programmed
4. Finally, after all words, or the entire block are
Status Register bit SR0 must be checked to determine
whether the program operation is finished. The Status
Register can be checked for errors at any time but must be
checked after the entire block is programmed.
Exit Phase
Status Register P/E.C. bit SR7 is set to ‘1’ when the device
exits the Buffer Enhanced Factory Program operation and
returns to Read Status Register mode. A full Status
Register check should be done to ensure that the block is
successfully programmed. See
for more details.
For optimum performance, the Buffer Enhanced Factory
Program command should be limited to a maximum of 100
program/erase cycles per block. If this limit is exceeded, the
internal algorithm continues to work properly, but some
degradation in performance is possible. Typical program
times are given in
See
the Buffer Enhanced Factory Program command.
Program/Erase Suspend Command
The Program/Erase Suspend command is used to pause a
Program or Block Erase operation. The command can be
addressed to any bank.
Address and the first word to be programmed. The
Status Register Bank Write Status bit SR0 should be
read to check that the P/E.C. is ready for the next word.
with a new Bus Write operation. The address must
remain the Start Address as the P/E.C. increments the
address location.If any address not in the same block
as the Start Address is given, the Program and Verify
Phase terminates. Status Register bit SR0 should be
read between each Bus Write cycle to check that the
P/E.C. is ready for the next word.
sequentially to the memory array. After the program
operation, the device automatically verifies the data and
reprograms if necessary.
The Program and Verify phase can be repeated without
re-issuing the command to program an additional 32-
word locations as long as the address remains in the
same block.
programmed, one Bus Write operation must be written
to any address outside the block containing the Start
Address to terminate Program and Verify Phase.
Figure 45, page
Table 21, page
79, for a suggested flowchart on using
"Status Register," page 23
44.
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