XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 29

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

X-Ref Target - Figure 11
Notes:
1.
2.
3.
X-Ref Target - Figure 12
Notes:
1.
2.
3.
DS617 (v3.0.1) January 07, 2010
Product Specification
READY_WAIT
READY_WAIT
DQ15–DQ0
V
W is tied High.
Address is latched on the third rising edge of K when G and E are Low, and L and READY_WAIT are High.
READY_WAIT requires an external pull-up resistor to V
when the READY_WAIT pin is released to a high-impedance state.
It is recommended to use the shown timings in the case of a free-running clock.
W is tied High.
K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at V
DQ15-DQ0
DD
V
A22–A0
DD
/V
A22-A0
DDQ
/V
DDQ
R
G
K
G
L
K
L
Address not Valid
T
T
VHRWZ
T
AVRWH
RWRT
T
RWHKL
T
VHRWZ
First Address Latching Sequence
T
Figure 12: Power-Up (Free-Running Clock)
RWRT
T
AVKH3
1
K1
2
DDQ
Address
Figure 11: Power-Up
Platform Flash XL High-Density Configuration and Storage Device
2
sufficiently strong to ensure a clean Low-to-High transition within less than T
3
www.xilinx.com
3
FFFFh (Sync + Dummy cycle)
T
4
FFFFh
4
KH3AX
Latency cycles (default = 7)
Latency Cycles
Valid Address
(default = 7)
T
T
RWHAX
KHQV
T
D0
KHQV
D1
D2
D0
D3
D1
D4
D2
D5
D3
IH
D6
and G at V
DS617_44_053008
DS617_45_101508
D4
D7
D5
D8
RWRT
IL
29
).