XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 26

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Wrap Burst Bit (CR3)
The Wrap Burst bit (CR3) is used to select between wrap
and no wrap. Synchronous burst reads can be confined
inside the 4, 8 or 16-word boundary (wrap) or overcome the
boundary (no wrap). When this bit is Low (set to ‘0’), the
burst read wraps. When it is High (set to ‘1’), the burst read
does not wrap.
Burst Length Bits (CR2-CR0)
The Burst Length bits are used to set the number of words
to be output during a Synchronous Burst Read operation as
result of a single address latch cycle. These bits can be set
for 4 words, 8 words, 16 words or continuous burst, where
all the words are read sequentially. In continuous burst
mode, the burst sequence can cross bank boundaries.
X-Ref Target - Figure 9
DS617 (v3.0.1) January 07, 2010
Product Specification
DQ15–DQ0
A22–A0
K
E
L
R
T
DELAY
VALID ADDRESS
Figure 9: X-Latency and Data Output Configuration Example
1 st cycle
T
AVK_CPU
2 nd cycle
Platform Flash XL High-Density Configuration and Storage Device
www.xilinx.com
X-latency
T
ACC
3 rd cycle
In continuous burst mode, or 4, 8 or 16 words no-wrap,
depending on the starting address, the device asserts the
WAIT signal to indicate that a delay is necessary before the
data is output.
If the starting address is shifted by 1, 2 or 3 positions from
the four-word boundary, WAIT is asserted for 1, 2 or 3 clock
cycles, respectively, when the burst sequence crosses the
first 16-word boundary, to indicate that the device needs an
internal delay to read the successive words in the array.
WAIT is asserted only once during a continuous burst
access. See also
CR14 and CR5 are reserved for future use.
4 th cycle
T
Table 14, page
QVK_CPU
VALID DATA
T
KQV
29.
T
VALID DATA
K
DS617_42_032508
T
QVK_CPU
26