XCF128XFTG64C Xilinx Inc, XCF128XFTG64C Datasheet - Page 37

• Manufacturer Part Number: XCF128XFTG64C
• Description: IC PROM SRL 128M GATE 64-FTBGA
• Manufacturer: Xilinx Inc

Specifications of XCF128XFTG64C

• Memory Size: 128Mb
• Programmable Type: In System Programmable
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Access Time: 85ns
• Supply Voltage Range: 1.7V To 2V
• Memory Case Style: FTBGA
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +85°C
• Svhc: No SVHC (15-Dec-2010)
• Package /: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1578

Power-On Reset
To ensure a correct power-up sequence of Platform Flash
XL, the V
200 μs or longer than 50 ms during power-up (see
page
values for which the power-up current is in the range where
the V
The device requires that the V
monotonically rises to the nominal operating voltage within
the specified V
this requirement, then the device might not perform power-
on reset properly.
During the POR sequence or a reset pulse (RP), the
READY_WAIT pin is held Low by the device. After the
required supply voltages (V
X-Ref Target - Figure 17
Notes:
1.
DS617 (v3.0.1) January 07, 2010
Product Specification
READY_WAIT
DQ15–DQ0
W is tied High.
DD
40). These timing limits correspond to the ramp rate
V
DD
A22-A0
ramp time is formally characterized or tested.
DD
/V
DDQ
R
ramp time, T
G
K
L
DD
rise time. If the power supply cannot meet
Address not Valid
T
VHRWZ
VDDPOR
Figure 17: Power-Up Sequence (System with Free-Running Clock)
DD
DD
T
and V
RWRT
, must not be shorter than
power supply
DDQ
T
AVKH3
) have reached
1
Valid Address
2
FFFFh (Sync + Dummy Cycle)
Figure 18,
Platform Flash XL High-Density Configuration and Storage Device
3
www.xilinx.com
4
T
Latency Cycles (default = 7)
KH3AX
their respective POR thresholds, the READY_WAIT pin is
released after a minimum time of t
supplies an additional margin for them to stabilize before
initiating the configuration.
For systems using a slow-rising power supply, an additional
power-monitoring circuit can be used to delay the release of
the READY_WAIT pin.
If the power drops below the power-down threshold
(V
held Low again until the POR threshold is reached (see
Figure 18
The power-up sequences with and without free-running
clock are represented in
DDPD
), the device is reset and the READY_WAIT pin is
for an illustration).
T
KHQV
Figure 11, page 31
D0
D1
RWL
D2
, to give the power
D3
and
D4
Figure
DS617_13_053008
D5
17.
37