Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 166

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Noise Filter
PS022008-0810
System
Clock
Architecture
LIN-UART
When configured as a general purpose timer, the BRG interrupt interval is calculated using
the following equation:
A noise filter circuit is included, which filters noise on a digital input signal such as UART
receive data before the data is sampled by the block. This is a requirement for protocols
with a noisy environment.
The noise filter includes following features:
•
•
•
•
•
Figure 29
network.
UART BRG Interrupt Interval (s)
Noise filter enable (
Provides an active low saturated state output (
Synchronizes the receive input data to the system clock.
Noise filter control (
The digital filter output has hysteresis.
or included (
counter digital filter. The available widths range is from 4 to11 bits.
noise.
displays how the noise filter is integrated with the LIN-UART for use on a LIN
NFEN, NFCTL
NFEN
FiltSatB
RxD
TxD
NFEN)
= 1) in the receive data path.
NFCTL[2:0])
P R E L I M I N A R Y
input selects whether the noise filter is bypassed (
Noise Filter
input selects the width of the up/down saturating
=
System Clock Period (s) BRG[15:0]
FiltSatB
), used to indicate presence of
TxD
RxD
Product Specification
ZNEO
RxD
TxD
Transceiver

Z16F Series
LIN
NFEN
LIN-UART
= 0)
150