Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 296

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
DMA Priority
6. After the reads have been completed, the DMA starts looking for requests and transfer
7. When the DMA receives the Request EOF signal, it does the following based upon the
8. If the
9. Once a new DMAxLAR address has been updated, the DMA goes back to step 2
The DMA priority is based upon the last channel serviced. Once a channel is serviced it
becomes the lowest priority channel.
Table 142. DMA Priority
Each DMA has equal priority under this scheme.
Last Channel Serviced
DMA0
DMA1
DMA2
DMA3
data until the transfer length reaches zero or the DMA receives a Request EOF signal.
LOOP
–
–
–
descriptor.
above and fetches the control/status byte.
00: The DMA writes the descriptor Control/Status word with the
to zero.
01: The DMA requests status from the peripheral. It then writes the descriptor
Control/Status word with the
the peripheral. The DMA then writes the TXLN length to the descriptor.
1X: The DMA does not modify the descriptor.
HALT
and
EOF
bit is set the DMA closes the current buffer but does not fetch the next
bit:
P R E L I M I N A R Y
DMA Priority
DMA1 (Highest)
DMA2
DMA3
DMA0 (Lowest)
DMA2 (Highest)
DMA3
DMA0
DMA1 (Lowest)
DMA3 (Highest)
DMA0
DMA1
DMA2 (Lowest)
DMA 0 (Highest)
DMA 1
DMA 2
DMA 3 (Lowest)
DMAxEN
Table 142
bit reset to zero and the status returned from
lists the DMA priority.
Product Specification
ZNEO
DMAxEN
DMA Controller
Z16F Series
bit reset
280