Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 261

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
ADC Clock
SAMPLE/HOLD
Internal signal
Internal signal
BUSY
ADC Timing
START bit
BUSY
Each ADC measurement consists of three phases:
1. Input sampling (programmable, minimum of 1.0 s).
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 s).
3. Conversion is 12 ADCLK cycles.
Figure 52
Figure 53
put.
1
2
displays the timing of an ADC conversion.
displays the timing of convert period showing the 10 bit progression of the out-
3
set by user
4
sample period
1.0 uS min
Figure 52. ADC Timing Diagram
Figure 53. ADC Convert Timing
5
convert period
6
12 clocks
P R E L I M I N A R Y
7
8
9
settling period
Programable
10
11
12
conversion period
13
cleared by BUSY
Product Specification
14
convert period
ZNEO
12 clock
15
Analog Functions
16
Z16F Series
17
245