C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 170
![DEV KIT FOR F040/F041/F042/F043](/photos/9/25/92582/c8051f040dk_sml.jpg)
C8051F040DK
Manufacturer Part Number
C8051F040DK
Description
DEV KIT FOR F040/F041/F042/F043
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F040DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F040
Silicon Family Name
C8051F04x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1205
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F040DK
Manufacturer:
SiliconL
Quantity:
9
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C8051F040/1/2/3/4/5/6/7
170
Bit7:
Bit6:
Bit5:
Bit0:
Bit4:
Bit3:
Bit2:
Bit1:
Bit7
R
-
Reserved.
CNVRSEF: Convert Start Reset Source Enable and Flag
Write:
Read:
C0RSEF: Comparator0 Reset Enable and Flag.
Write:
Read:
SWRSF: Software Reset Force and Flag.
Write:
Read:
WDTRSF: Watchdog Timer Reset Flag.
MCDRSF: Missing Clock Detector Flag.
Write:
detected.
Read:
PORSF: Power-On Reset Flag.
Write: If the
bit can be written to select or de-select the
0: De-select the
1: Select the
Important: At power-on, the V
tor enable pin (MONEN). The PORSF bit does not disable or enable the V
cuit. It simply selects the V
Read: This bit is set whenever a power-on reset occurs. This may be due to a true power-on
reset or a V
following the reset.
0: Source of last reset was not a power-on or V
1: Source of last reset was a power-on or V
Note: When this flag is read as '1', all other reset flags are indeterminate.
PINRSF: HW Pin Reset Flag.
Write:
Read:
CNVRSEF C0RSEF SWRSEF WDTRSF MCDRSF
R/W
Bit6
0: CNVSTR0 is not a reset source.
1: CNVSTR0 is a reset source (active low).
0: Source of prior reset was not CNVSTR0.
1: Source of prior reset was CNVSTR0.
0: Comparator0 is not a reset source.
1: Comparator0 is a reset source (active low).
0: Source of last reset was not Comparator0.
1: Source of last reset was Comparator0.
1: Forces an internal reset. /RST pin is not effected.
0: Source of last reset was not a write to the SWRSF bit.
1: Source of last reset was a write to the SWRSF bit.
0: Source of last reset was not WDT timeout.
1: Source of last reset was WDT timeout.
0: No effect.
1: Forces a Power-On Reset. /RST is driven low.
0: Source of prior reset was not /RST pin.
1: Source of prior reset was /RST pin.
0: No effect.
0: Missing Clock Detector disabled.
1: Missing Clock Detector enabled; triggers a reset if a missing clock condition is
0: Source of last reset was not a Missing Clock Detector timeout.
1: Source of last reset was a Missing Clock Detector timeout.
DD
V
SFR Definition 13.2. RSTSRC: Reset Source
V
DD
DD
monitor reset. In either case, data memory should be considered indeterminate
V
monitor circuitry is enabled (by tying the MONEN pin to a logic high state), this
R/W
Bit5
DD
monitor as a reset source.
monitor as a reset source.
DD
R/W
Bit4
DD
monitor as a reset source.
monitor is enabled/disabled using the external V
Rev. 1.5
Bit3
R
V
DD
DD
monitor reset.
DD
monitor as a reset source.
monitor reset.
R/W
Bit2
PORSF
Bit1
R
SFR Address:
PINRSF
SFR Page:
R/W
Bit0
DD
monitor cir-
0xEF
0
00000000
Reset Value
DD
moni-
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