C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 6

• Manufacturer Part Number: C8051F040DK
• Description: DEV KIT FOR F040/F041/F042/F043
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F040
• Silicon Family Name: C8051F04x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1205

C8051F040/1/2/3/4/5/6/7
19. System Management BUS/I
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 255
21. UART0.................................................................................................................... 265
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18.2.CAN Registers................................................................................................ 231
19.1.Supporting Documents ................................................................................... 240
19.2.SMBus Protocol.............................................................................................. 241
19.3.SMBus Transfer Modes.................................................................................. 242
19.4.SMBus Special Function Registers ................................................................ 245
20.1.Signal Descriptions......................................................................................... 256
20.2.SPI0 Master Mode Operation ......................................................................... 257
20.3.SPI0 Slave Mode Operation ........................................................................... 259
20.4.SPI0 Interrupt Sources ................................................................................... 259
20.5.Serial Clock Timing......................................................................................... 260
20.6.SPI Special Function Registers ...................................................................... 261
21.1.UART0 Operational Modes ............................................................................ 266
21.2.Multiprocessor Communications .................................................................... 270
18.1.2.Example Timing Calculation for 1 Mbit/Sec Communication ................. 229
18.2.1.CAN Controller Protocol Registers......................................................... 231
18.2.2.Message Object Interface Registers ...................................................... 231
18.2.3.Message Handler Registers................................................................... 232
18.2.4.CIP-51 MCU Special Function Registers ............................................... 232
18.2.5.Using CAN0ADR, CAN0DATH, and CANDATL to Access CAN Registers .
18.2.6.CAN0ADR Autoincrement Feature ........................................................ 232
19.2.1.Arbitration............................................................................................... 241
19.2.2.Clock Low Extension.............................................................................. 242
19.2.3.SCL Low Timeout................................................................................... 242
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 242
19.3.1.Master Transmitter Mode ....................................................................... 242
19.3.2.Master Receiver Mode ........................................................................... 243
19.3.3.Slave Transmitter Mode ......................................................................... 243
19.3.4.Slave Receiver Mode ............................................................................. 244
19.4.1.Control Register ..................................................................................... 245
19.4.2.Clock Rate Register ............................................................................... 248
19.4.3.Data Register ......................................................................................... 249
19.4.4.Address Register.................................................................................... 249
19.4.5.Status Register....................................................................................... 250
20.1.1.Master Out, Slave In (MOSI).................................................................. 256
20.1.2.Master In, Slave Out (MISO).................................................................. 256
20.1.3.Serial Clock (SCK) ................................................................................. 256
20.1.4.Slave Select (NSS) ................................................................................ 256
21.1.1.Mode 0: Synchronous Mode .................................................................. 266
21.1.2.Mode 1: 8-Bit UART, Variable Baud Rate.............................................. 267
21.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate .................................................. 269
21.1.4.Mode 3: 9-Bit UART, Variable Baud Rate.............................................. 270
232
2
C BUS (SMBUS0) .................................................. 239
Rev. 1.5