C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 240

DEV KIT FOR F040/F041/F042/F043

C8051F040DK

Manufacturer Part Number
C8051F040DK
Description
DEV KIT FOR F040/F041/F042/F043
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F040DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F040
Silicon Family Name
C8051F04x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1205

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C8051F040/1/2/3/4/5/6/7
Figure 19.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between
3.0 V and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional
SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high when the bus is free.
The maximum number of devices on the bus is limited only by the requirement that the rise and fall times
on the bus will not exceed 300 ns and 1000 ns, respectively.
19.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
240
I
System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
2
C Manual (AN10216-01) -- March 24, 2003, Philips Semiconductor.
V
DD
= 5 V
Figure 19.2. Typical SMBus Configuration
V
Master
Device
DD
= 3 V
Rev. 1.5
Device 1
V
Slave
DD
= 5 V
Device 2
V
Slave
DD
= 3 V
SDA
SCL

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