C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 225

• Manufacturer Part Number: C8051F040DK
• Description: DEV KIT FOR F040/F041/F042/F043
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F040
• Silicon Family Name: C8051F04x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1205

Bits7-0:
Note:
Bits7-0:
Note:
P7.7
R/W
R/W
Bit7
Bit7
P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P7MDOUT bit = 0). See SFR Definition
17.23.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See
Interface and On-Chip XRAM” on page 187
ory Interface.
P7MDOUT.[7:0]: Port7 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
P7.6
R/W
R/W
Bit6
Bit6
SFR Definition 17.23. P7MDOUT: Port7 Output Mode
P7.5
R/W
R/W
Bit5
Bit5
SFR Definition 17.22. P7: Port7 Data
P7.4
R/W
R/W
Bit4
Bit4
Rev. 1.5
P7.3
R/W
R/W
Bit3
Bit3
C8051F040/1/2/3/4/5/6/7
for more information about the External Mem-
P7.2
R/W
R/W
Bit2
Bit2
Section “16. External Data Memory
P7.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P7.0
R/W
R/W
Bit0
Bit0
0xF8
F
0x9F
F
Addressable
Reset Value
00000000
Reset Value
11111111
Bit
225