DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 118

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 6: Implementing FPGA Designs
108
constraint. For this design, assume that the specification for clock frequency is 100 MHz
and that the pin-out has been pre-determined to that of a Spartan-3 device.
There are already some constraints in the UCF from the previous project implementation.
It will be necessary to delete these constraints before running Implementation steps. This is
because we set constraints that apply only to CPLDs, and set pin-outs for a CoolRunner-II
XC2C256-TQ144.
1.
2.
3.
4.
5.
Note:
<> or XST Optional {}.
6.
Highlight “top.ucf” in the Source window. Expand the plus sign(+) next to User
Constraints and double-click Edit Constraints (Text).
Highlight all of the constraints (the entire file) and delete them. Save the UCF
(File → Save).
Double-click on Assign Package Pins. Alternatively, you can highlight the top
level file (“top.vhd”) and expand the User Constraints branch.
The PACE tool will be launched.
In PACE, assign all I/O pins in the Design Object List as shown in
Simply place the cursor in the Loc column, click on the entry for each, and type in the
values shown. If you have selected another package type, you can refer to the data
sheet, or roll over the package pins in the PACE display to find a global clock pin for
clock.
Save (File → Save) and Exit (File → Exit)the PACE session.
Double-click on Create Timing Constraints in the Process window.
You may encounter a dialog that asks you to define the bus delimiter. Select XST Default:
Figure 6-7: Process Window Showing Assign Package Pins
www.xilinx.com
Figure 6-8: Design Object List
Programmable Logic Design
Figure
June 12, 2006
6-8.
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