DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 12

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Chapter 1:
2
MMI (later purchased by AMD™) was enlisted as a second source for the PLA array. After
fabrication issues, it was modified to become the programmable array logic (PAL)
architecture by fixing one of the programmable planes.
This new architecture differed from that of the PLA in that one of the programmable planes
was fixed – the OR array. PAL architecture also had the added benefit of faster t
complex software, but without the flexibility of the PLA structure.
Other architectures followed, such as the PLD. This category of devices is often called
Simple PLD.
•
•
•
•
•
The architecture had a mesh of horizontal and vertical interconnect tracks. At each junction
was a fuse. With the aid of software tools, designers could select which junctions would
not be connected by “blowing” all unwanted fuses. (This was done by a device
programmer, but more commonly these days is achieved with ISP).
Input pins were connected to the vertical interconnect. The horizontal tracks were
connected to AND-OR gates, also called “product terms”. These in turn connected to
dedicated flip-flops, whose outputs were connected to output pins.
PLDs provided as much as 50 times more gates in a single package than discrete logic
devices! This was a huge improvement, not to mention fewer devices needed in inventory
and a higher reliability over standard logic.
PLD technology has moved on from the early days with companies such as Xilinx
producing ultra-low-power CMOS devices based on flash memory technology. Flash
One programmable plane: AND/Fixed OR
Finite combination of ANDs/ORs
Medium logic density available to user
Lower fuse count; faster than PLAs (at the time, fabricated on a 10 μM process)
Programmable array logic
A
A
Indicates ‘used’ junction
Indicates ‘used’ junction
Indicates ‘used’ junction
Indicates ‘unused’ junction
Indicates ‘unused’ junction
Indicates ‘unused’ junction
Indicates ‘unused’ junction
Indicates ‘fixed’ junction
Indicates ‘fixed’ junction
Indicates ‘fixed’ junction
Indicates ‘fixed’ junction
Inputs
Inputs
B
B
C
C
Figure 1-2: SPLD Architectures (PAL)
www.xilinx.com
Outputs have dedicated product terms
Outputs have dedicated product terms
X
X
Outputs
Outputs
Y
Y
Programmable Logic Design
Requires 4 pt’s
Requires 4 pt’s
X = A & B # C
X = A & B # C
Y = A & B # !C
Y = A & B # !C
June 12, 2006
PD
and less
R