DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 35

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

Programmable Logic Design
June 12, 2006
R
The Spartan-3 FPGA memory architecture provides the optimal granularity and efficient
area utilization.
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Shift Register SRL16 Blocks
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As Much as 520 Kb Distributed SelectRAM™ Memory
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As Much as 1.87 Mb Embedded Block RAM
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Memory Interfaces
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Multipliers
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Each CLB LUT works as a 16-bit fast, compact shift register
Cascade LUTs to build longer shift registers
Implement pipeline registers and buffers for video or wireless
Each LUT works as a single-port or dual-port RAM/ROM
Cascade LUTs to build larger memories
Applications include flexible memory sizes, FIFOs, and buffers
As many as 104 blocks of synchronous, cascadable 18 Kb block RAM
Configure each 18 Kb block as a single- or dual-port RAM
Supports multiple aspect ratios, data-width conversion, and parity
Applications include data caches, deep FIFOs, and buffers
Enable electrical interfaces such as HSTL and SSTL to connect to popular external
memories
Enable simple arithmetic and math as well as advanced DSP functions, enabling
you to derive more than 330 billion MACs/s of DSP performance
Figure 2-17: Spartan-3 Configurable Logic Block
www.xilinx.com
Switch
Switch
Matrix
Matrix
SHIFT
SHIFT
SLICEM S1
SLICEM S1
SLICEM S0
SLICEM S0
X0Y1
X0Y1
X0Y0
X0Y0
COUT
COUT
CIN
CIN
SLICEL S3
SLICEL S3
SLICEL S2
SLICEL S2
X1Y1
X1Y1
X1Y0
X1Y0
COUT
COUT
CIN
CIN
Platform FPGAs
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