DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 136

• Manufacturer Part Number: DO-CPLD-DK-G
• Description: KIT DESIGN CPLD W/BATT HOLDER
• Manufacturer: Xilinx Inc
• Series: CoolRunner™- IIr
• Type: CPLDr

Specifications of DO-CPLD-DK-G

• Contents: Proto Board, Download Cable, Samples, Software
• For Use With/related Products: CoolRunner-ll, XC9500XL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1512

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Compiler – software that converts a higher language description into a lower-level
representation. For FPGAs: the complete partition, place and route process.
Configuration – The internally stored file that controls the FPGA so that it performs the
desired logic function. Also, the act of loading an FPGA with that file.
Constraints – Performance requirements imposed on the design, usually in the form of
max allowable delay, or required operating frequency.
CoolCLOCK – Combination of the clock divider and clock doubler functions in
CoolRunner-II CPLDs to further reduce power consumption associated with high-speed
clocked-in internal device networks.
CPLD – Complex Programmable Logic Device, synonymous with EPLD. PAL-derived
programmable logic devices that implement logic as sum-of- products driving macrocells.
CPLDs are known to have short pin-to-pin delays, and can accept wide inputs, but have
relatively high power consumption and fewer flip-flops compared to FPGAs.
CUPL – Compiler Universal for Programmable Logic, CPLD development tool available
from Logical Devices.
DataGATE – A function within CoolRunner-II devices to block free-running input signals,
effectively blocking controlled switching signals so they do not drive internal chip
capacitances to further reduce power consumption. Can be selected on all inputs.
Input Hysteresis – Input hysteresis provides designers with a tool to minimize external
components, whether using the inputs to create a simple clock source or reducing the need
for external buffers to sharpen a slow or noisy input signal. Function found in CoolRunner-
II CPLDs (may also be referred to as Schmitt Trigger inputs in the text).
DCM – Digital Clock Manager. Provides zero-delay clock buffering, precise phase control,
and precise frequency generation on Xilinx Virtex-II FPGAs.
DCI – Digitally Controlled Impedance in the Virtex-II solution dynamically eliminates drive
strength variation due to process, temperature, and voltage fluctuation. DCI uses two
external high-precision resistors to incorporate equivalent input and output impedance
internally for hundreds of I/O pins.
Debugging – The process of finding and eliminating functional errors in software and
hardware.
Density – Amount of logic in a device, often used to mean capacity. Usually measured in
gates, but for FPGAs, better expressed in logic cells, each consisting of a 4-input LUT and
a flip-flop.
DLL – Delay Locked Loop, A digital circuit used to perform clock management functions
on- and off-chip.
DRAM – Dynamic Random Access Memory. A low-cost/read-write memory where data is
stored on capacitors and must be refreshed periodically. DRAMs are usually addressed by
a sequence of two addresses – row address and column address – which makes them
slower and more difficult to use than SRAMs.
DSP – Digital Signal Processing. The manipulation of analog data that has been sampled
and converted into a digital representation. Examples are filtering, convolution, and Fast
Fourier Transform
EAB – Embedded Array Block. Altera™ name for block RAM in FLEX10K.
EDIF – Electronic Data Interchange Format. Industry-standard for specifying a logic design
in text (ASCII) form.
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Programmable Logic Design
June 12, 2006