DO-CPLD-DK-G Xilinx Inc, DO-CPLD-DK-G Datasheet - Page 99
![KIT DESIGN CPLD W/BATT HOLDER](/photos/9/26/92617/do-cpld-dk-g_sml.jpg)
DO-CPLD-DK-G
Manufacturer Part Number
DO-CPLD-DK-G
Description
KIT DESIGN CPLD W/BATT HOLDER
Manufacturer
Xilinx Inc
Series
CoolRunner™- IIr
Type
CPLDr
Specifications of DO-CPLD-DK-G
Contents
Proto Board, Download Cable, Samples, Software
For Use With/related Products
CoolRunner-ll, XC9500XL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1512
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Constraints Editor
Programmable Logic Design
June 12, 2006
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To get the performance you need from a device, you must tell the implementation tools
what and where performance is required. This design is particularly slow and timing
constraints are unnecessary. Constraints can also be physical; pin locking is a physical
constraint. For this design, assume that the specification for clock frequency is 100 MHz
and that the placement of pins will be suitable for a CoolRunner-II on a pre-designed
board.
1.
A window appears allowing you to influence the way in which your design is
interpreted. The Help feature will explain each of the options in each tab.
Highlight the Xilinx Specific Options category.
In the Xilinx Specific Options tab, ensure that the Add IO Buffers box is ticked. The
I/O buffers will be attached to all the port names in the top-level entity of the design.
Clicking on Help in each tab demonstrates the complex issue of synthesis and how the
final result could change. The synthesis tool will never alter the function of the design,
but it has a huge influence on how the design will perform in the targeted device.
Click OK in the Process Properties window and double-click on Synthesize.
When the synthesis is complete, a green tick will appear next to Synthesize. Double-
click on View Synthesis Report. The report file (.syr) will appear in ISE.
In the Process window, expand the User Constraints tree and double-click
Assign Package Pins. As there is no constraints file present in the design, the
Figure 5-3: Process Properties for Xilinx Specific Options
www.xilinx.com
Constraints Editor
89
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